1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a transistor and a method for manufacturing the same, that provides a tensile stress by forming a gate spacer of containing nitrogen.
2. Discussion of the Related Art
A method for manufacturing a transistor according to the related art will be described as follows.
FIG. 1A to FIG. 1E are cross sectional views for explaining a method of forming a transistor in a semiconductor device according to the related art.
As shown in FIG. 1A, a device isolation layer 12 is formed in a device isolation region of a semiconductor substrate 11. The device isolation layer 12 is a Shallow Trench Isolation (STI) structure. Subsequently, n-type and p-type wells (not shown) are formed in active regions of the substrate 11, according to the channel type of the transistor. In order to control a threshold voltage of the transistor, p-type and n-type impurity ions are selectively implanted in a channel ion implantation process, whereby a channel ion implant layer (not shown) is formed at a predetermined depth of the well. After forming the n-type well, the p-type well, and the channel ion implantation layer, a thermal process is performed to activate the implanted impurity ions.
After that, an oxide layer 13a and a polysilicon layer 14a are sequentially formed on the semiconductor substrate 11. With increasing integration of the device, the thickness of the oxide layer 13a generally decreases. A thin oxide layer 13a may generate, increase or result in a leakage current. In order to reduce or prevent the leakage current, nitrogen may be injected to the oxide layer 13a, thereby decreasing the electrical thickness and increasing the physical thickness.
As shown in FIG. 1B, the oxide layer 13a and the polysilicon layer 14a are patterned by an etch process using a gate mask, thereby forming a gate oxide layer 13 and a gate electrode 14. Then, in order to prevent the increase of a depletion layer in source and drain regions, a pocket region 15 is formed in a pocket ion implantation process. The pocket region 15 may be formed in a tilt-ion implantation process using the gate electrode 14 as a mask.
Before performing the pocket ion implantation process, a buffer oxide layer (not shown) having a uniform thickness is formed on the semiconductor substrate 11 having the gate electrode 14 by a thermal oxidation process, thereby preventing or reducing damage to the transistor due to the ion implantation. Next, a relatively low dose or concentration of impurity ions are implanted into the semiconductor substrate 11 using the gate electrode 14 as a mask, thereby forming lightly-doped (LDD) regions 16a in the semiconductor substrate 11 adjacent to gate 14 (e.g., at both sides of the gate electrode 14 as shown).
As shown in FIG. 1C, an insulating layer of TEOS (tetraethyl orthosilicate)-based glass is formed on an entire surface of the semiconductor substrate 11, including the gate electrode 14, at a predetermined thickness, thereby forming a buffer layer 17. Thereon, a silicon nitride layer 18 and a TEOS oxide layer 19 are sequentially formed (e.g., for subsequent formation of a double spacer). At this time, the buffer layer 17 may have a thickness of 200 Å, the silicon nitride layer 18 may have a thickness of 200 Å, and the TEOS oxide layer 19 may have a thickness of 800 Å. Or, the buffer layer 17 may have a thickness of 100 Å, the silicon nitride layer 18 may have a thickness of 100 Å, and the TEOS oxide layer 19 may have a thickness of 800 Å.
Referring to FIG. 1D, spacers 21 and 22 (including layers 17, 18 and 19) are formed at sidewalls of the gate electrode 14 by anisotropically etching the TEOS oxide layer 19, the silicon nitride layer 18 and the buffer layer 17. Then, a relatively high dose or concentration of impurity ions are implanted into the semiconductor substrate using the gate electrode 14 and the spacers 21 and 22 as a mask, thereby forming highly-doped ion implantation layers 16b adjacent to the spacers 21 and 22. Then, a thermal process is performed thereto, thereby activating the implanted impurity ions. Accordingly, it is possible to form source and drain regions 16 comprised of the LDD regions 16a and the highly-doped ion implantation layers 16b. 
As shown in FIG. 1E, in order to lower a contact resistance, a silicide layer 20 is formed on the gate electrode 14 and the source and drain regions 16, thereby forming the transistor.
However, the method for manufacturing the transistor according to the related art has some disadvantages. In order to prevent or reduce the leakage current, nitrogen may be injected into the gate oxide layer. As the density of nitrogen increases, it is advantageous to a PMOS transistor. However, an increase in the density of nitrogen is disadvantageous to an NMOS transistor since the mobility of electrons moving from the source region to the drain region decreases. On the other hand, the electron, which is the carrier of the NMOS transistor, has great mobility under tensile stress.
Also, the silicon nitride layer in the spacer has a tensile stress of about 1010 dynes/cm2, but the TEOS oxide layer scarcely has any tensile stress. However, in the entire spacer, since the TEOS oxide layer is the main part, the spacer has at most a small tensile stress, so that it may be difficult to improve the On-current (also known as “on-state current”) or carrier mobility.
However, since silicon nitride has a relatively high tensile stress, it is possible to improve the tensile stress in the spacer by forming a thin silicon nitride layer. However, it may be impossible to form a thin silicon nitride layer under some conditions, since a thin silicon nitride layer may generate other problems.